The present invention relates to technique of a semiconductor device. More particularly, the present invention relates to technique which is effective when applied to a semiconductor device in which a plurality of semiconductor chips having different planar sizes are stacked.
Japanese Patent Application Laid-Open Publication No. 2011-187574 (Patent Document 1) describes a semiconductor device in which a semiconductor chip having through silicon vias is disposed between a stacked body of a plurality of memory chips and a wiring board.
Japanese Patent Application Laid-Open Publication No. 2008-91638 (Patent Document 2) and Japanese Patent Application Laid-Open Publication No. 2008-91640 (Patent Document 3) describe a semiconductor device in which a plurality of semiconductor chips including a stacked body of a plurality of semiconductor chips are mounted on a wiring board and collectively sealed.
Japanese Patent Application Laid-Open Publication (Translation of PCT Application) No. 2010-538358 (Patent Document 4) describes methods of stacking a plurality of semiconductor chips including stacking at wafer level and stacking at chip level.